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NS E SI G W D A RT NE NT P FO R D E D LA C E M E EN M M D R EP Data Sheet EC O E C OT R MMEND L62884 N S I O R EC
(R)
ISL6261A
November 5, 2009 FN6354.3
Single-Phase Core Regulator for IMVP-6(R) Mobile CPUs
The ISL6261A is a single-phase buck regulator implementing lntel(R) IMVP-6(R) protocol, with embedded gate drivers. lntel(R) Mobile Voltage Positioning (IMVP) is a smart voltage regulation technology effectively reducing power dissipation in lntel(R) Pentium processors. The heart of the ISL6261A is the patented R3 TechnologyTM, Intersil's Robust Ripple Regulator modulator. Compared with the traditional multi-phase buck regulator, the R3 TechnologyTM has faster transient response. This is due to the R3 modulator commanding variable switching frequency during a load transient. The ISL6261A provides three operation modes: the Continuous Conduction Mode (CCM), the Diode Emulation Mode (DEM) and the Enhanced Diode Emulation Mode (EDEM). To boost battery life, the ISL6261A changes its operation mode based on CPU mode signals DPRSLRVR and DPRSTP#, and the FDE pin setting, to maximize the efficiency. In CPU active mode, the ISL6261A commands the CCM operation. When the CPU enters deeper sleep mode, the ISL6261A enables the DEM to maximize the efficiency at light load. Asserting the FDE pin of the ISL6261A in CPU deeper sleep mode will enable the EDEM to further decrease the switching frequency at light load and increase the regulator efficiency. A 7-bit Digital-to-Analog Converter (DAC) allows dynamic adjustment of the core output voltage from 0.300V to 1.500V. The ISL6261A has 0.5% system voltage accuracy over temperature. A unity-gain differential amplifier provides remote voltage sensing at the CPU die. This allows the voltage on the CPU die to be accurately measured and regulated per lntel(R) IMVP-6 specification. Current sensing can be implemented through either lossless inductor DCR sensing or precise resistor sensing. If DCR sensing is used, an NTC thermistor network will thermally compensates the gain and the time constant variations caused by the inductor DCR change. The ISL6261A provides the power monitor function through the PMON pin. PMON output is a high-bandwidth analog voltage signal representing the CPU instantaneous power. The power monitor function can be used by the system to optimize the overall power consumption, extending battery run time.
Features
* Precision single-phase CORE voltage regulator - 0.5% system accuracy over temperature - Enhanced load line accuracy * Internal gate driver with 2A driving capability * Microprocessor voltage identification input - 7-Bit VID input - 0.300V to 1.500V in 12.5mV steps - Support VID change on-the-fly * Multiple current sensing schemes supported - Lossless inductor DCR current sensing - Precision resistive current sensing * Thermal monitor * Power monitor indicating CPU instantaneous power * User programmable switching frequency * Differential remote voltage sensing at CPU die * Overvoltage, undervoltage, and overcurrent protection * Pb-free (RoHS compliant)
Ordering Information
PART NUMBER (Notes 2, 3) ISL6261ACRZ PART MARKING TEMP. RANGE (C) PACKAGE (Pb-Free) PKG. DWG. #
ISL6261 ACRZ -10 to +100 40 Ld 6x6 QFN L40.6x6
ISL6261ACRZ-T* ISL6261 ACRZ -10 to +100 40 Ld 6x6 QFN L40.6x6 (Note 1) Tape and Reel ISL6261AIRZ 6261A IRZ -40 to +100 40 Ld 6x6 QFN L40.6x6 -40 to +100 40 Ld 6x6 QFN L40.6x6 Tape and Reel
ISL6261AIRZ-T* 6261A IRZ (Note 1) NOTES:
1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6261A. For more information on MSL please see techbrief TB363.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2007, 2009. All Rights Reserved. R3 TechnologyTM is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
ISL6261A Pinout
ISL6261A (40 LD QFN) TOP VIEW
DPRSLPVR DPRSTP# CLK_EN PGOOD
VR_ON
VID6
VID5
VID4 32
40 FDE PMON RBIAS VR_TT# NTC SOFT OCSET VW COMP FB 1 2 3 4 5 6 7 8 9 10 11 VDIFF
39
38
37
36
35
34
33
VID3 31 30 VID2 29 VID1 28 VID0 27 VCCP 26 LGATE 25 VSSP 24 PHASE 23 UGATE 22 BOOT 21 NC 20 VDD
3V3
GND PAD (BOTTOM)
12 VSEN
13 RTN
14 DROOP
15 DFB
16 VO
17 VSUM
18 VIN
19 VSS
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FN6354.3 November 5, 2009
ISL6261A
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+28V Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V Boot to Phase Voltage (BOOT-PHASE). . . . . . . . . -0.3V to +7V(DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +9V(<10ns) Phase Voltage (PHASE) . . . . . . . . . -7V (<20ns Pulse Width, 10J) UGATE Voltage (UGATE) . . . . . . . . . . PHASE-0.3V (DC) to BOOT . . . . . . . . . . . . . .PHASE-5V (<20ns Pulse Width, 10J) to BOOT LGATE Voltage (LGATE) . . . . . . . . . . . . . . -0.3V (DC) to VDD+0.3V . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5J) to VDD+0.3V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V) Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . -0.3 to +7V
Thermal Information
Thermal Resistance (Typical, Notes 4, 5) JA (C/W) JC (C/W) QFN Package. . . . . . . . . . . . . . . . . . . . 33 6 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V 5% Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 21V Ambient Temperature ISL6261ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . .-10C to +100C ISL6261AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +100C Junction Temperature ISL6261ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . .-10C to +125C ISL6261AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +125C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VDD = 5V, TA = -40C to +100C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +100C. SYMBOL TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNITS
PARAMETER INPUT POWER SUPPLY +5V Supply Current
IVDD I3V3 IVIN PORr PORf
VR_ON = 3.3V VR_ON = 0V
3.85
3.1 4.35 4.1
3.6 1 1 1 4.5 -
mA A A A V V
+3.3V Supply Current Battery Supply Current at VIN Pin POR (Power-On Reset) Threshold
No load on CLK_EN# pin VR_ON = 0, VIN = 25V VDD rising VDD falling No load, close loop, active mode, TA =-10C to +100C, VID = 0.75V to 1.5V VID = 0.5V to 0.7375V VID = 0.3V to 0.4875V
SYSTEM AND REFERENCES System Accuracy %Error (Vcc_core) ISL6261ACRZ -0.5 -8 -15 -0.8 -10 -18 1.45 1.188 VID = [0000000] VID = [1100000] VID = [1111111] 1.47 1.2 1.5 0.3 0.0 0.5 8 15 0.8 10 18 1.49 1.212 % mV mV % mV mV V V V V V
%Error (Vcc_core) ISL6261AIRZ
No load, close loop, active mode, VID = 0.75V to 1.5V VID = 0.5V to 0.7375V VID = 0.3V to 0.4875V
RBIAS Voltage Boot Voltage Maximum Output Voltage Minimum Output Voltage VID Off State CHANNEL FREQUENCY Nominal Channel Frequency
RRBIAS VBOOT VCC_CORE (max) VCC_CORE (min)
RRBIAS = 147k
fSW
RFSET = 7k, Vcomp = 2V
318
333
348
kHz
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FN6354.3 November 5, 2009
ISL6261A
Electrical Specifications
VDD = 5V, TA = -40C to +100C, unless otherwise specified. (Continued) Boldface limits apply over the operating temperature range, -40C to +100C. (Continued) SYMBOL TEST CONDITIONS MIN (Note 7) 200 TYP MAX (Note 7) UNITS 500 kHz
PARAMETER Adjustment Range AMPLIFIERS Droop Amplifier Offset Error Amp DC Gain (Note 6) Error Amp Gain-Bandwidth Product (Note 6) Error Amp Slew Rate (Note 6) FB Input Current SOFT-START CURRENT Soft-start Current Soft Geyserville Current Soft Deeper Sleep Entry Current Soft Deeper Sleep Exit Current Soft Deeper Sleep Exit Current POWER MONITOR PMON Output Voltage Range
-0.3 AV0 GBW SR IIN(FB) ISS IGV IC4 IC4EA IC4EB VPMON VPMONMAX ISC_PMON ISK_PMON VSEN = 1V, VDROOP - VO = 25mV VSEN = 1V, VDROOP - VO = 25mV |SOFT - REF|>100mV DPRSLPVR = 3.3V DPRSLPVR = 3.3V DPRSLPVR = 0V CL = 20pF CL = 20pF -
90 18 5.0 10
0.3 150
mV dB MHz V/s nA
-47 180 -46 36 175
-42 205 -41 41 200
-37 230 -36 46 225
A A A A A
VSEN = 1.2V, VDROOP - VO = 40mV VSEN = 1V, VDROOP - VO = 10mV
1.638 0.308 2.8 2 2
1.680 0.350 3.0 -
1.722 0.392 PMON /130 -
V V V mA mA A
PMON Maximum Voltage PMON Sourcing Current PMON Sinking Current Maximum Current Sinking Capability PMON Impedance
PMON/250 PMON/180 ZPMON When PMON current is within its ourcing/sinking current range (Note 6) 7
GATE DRIVER DRIVING CAPABILITY (Note 6) UGATE Source Resistance UGATE Source Current UGATE Sink Resistance UGATE Sink Current LGATE Source Resistance LGATE Source Current LGATE Sink Resistance LGATE Sink Current UGATE to PHASE Resistance RSRC(UGATE) ISRC(UGATE) RSNK(UGATE) ISNK(UGATE) RSRC(LGATE) ISRC(LGATE) RSNK(LGATE) ISNK(LGATE) RP(UGATE) tPDHU ISL6261ACRZ tPDHU ISL6261AIRZ LGATE Turn-on Propagation Delay tPDHL ISL6261ACRZ tPDHL ISL6261AIRZ BOOTSTRAP DIODE Forward Voltage VDDP = 5V, forward bias current = 2mA 0.43 0.58 0.72 V TA = -10C to +100C, PVCC = 5V, output unloaded PVCC = 5V, output unloaded TA = -10C to +100C, PVCC = 5V, output unloaded PVCC = 5V, output unloaded 500mA source current VUGATE_PHASE = 2.5V 500mA sink current VUGATE_PHASE = 2.5V 500mA source current VLGATE = 2.5V 500mA sink current VLGATE = 2.5V 1 2 1 2 1 2 0.5 4 1.1 1.5 1.5 1.5 0.9 A A A A k
GATE DRIVER SWITCHING TIMING (Refer to "Gate Driver Timing Diagram" on page 6) UGATE Turn-on Propagation Delay 20 18 7 5 30 30 15 15 44 44 30 30 ns ns ns ns
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FN6354.3 November 5, 2009
ISL6261A
Electrical Specifications
VDD = 5V, TA = -40C to +100C, unless otherwise specified. (Continued) Boldface limits apply over the operating temperature range, -40C to +100C. (Continued) SYMBOL VR = 16V VOL IOH tpgd OVH OVHS IPGOOD = 4mA PGOOD = 3.3V CLK_EN# low to PGOOD high VO rising above setpoint > 1ms VO rising above setpoint > 0.5s I(RBIAS) = 10A DROOP rising above OCSET > 120s UVf VO below set point for > 1ms TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNITS 1 A
PARAMETER Leakage
POWER GOOD and PROTECTION MONITOR PGOOD Low Voltage PGOOD Leakage Current PGOOD Delay Overvoltage Threshold Severe Overvoltage Threshold OCSET Reference Current OC Threshold Offset Undervoltage Threshold (VDIFF-SOFT) LOGIC THRESHOLDS VR_ON and DPRSLPVR Input Low VR_ON and DPRSLPVR Input High Leakage Current on VR_ON VIL(3.3V) VIH(3.3V) IIL IIH Leakage Current on DPRSLPVR IIL_DPRSLP IIH_DPRSLP DAC(VID0-VID6), PSI# and DPRSTP# Input Low DAC(VID0-VID6), PSI# and DPRSTP# Input High Leakage Current of DAC(VID0-VID6) and DPRSTP# THERMAL MONITOR NTC Source Current Over-temperature Threshold VR_TT# Low Output Resistance CLK_EN# OUTPUT LEVELS CLK_EN# High Output Voltage CLK_EN# Low Output Voltage NOTES: 6. Limits established by characterization and are not production tested. 7. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. VOH VOL 3V3 = 3.3V, I = -4mA ICLK_EN# = 4mA 2.9 3.1 0.18 0.4 V V RTT NTC = 1.3 V V(NTC) falling I = 20mA 53 1.17 60 1.2 5 67 1.25 9 A V VIL(1.0V) VIH(1.0V) IIL IIH DPRSLPVR logic input is low DPRSLPVR logic input is high Logic input is low Logic input is high DPRSLPVR logic input is low DPRSLPVR logic input is high 2.3 -1 -1 0.7 -1 0 0 0 0.45 0 0.45 1 1 1 0.3 1 V V A A A A V V A A -1 5.5 155 1.675 9.8 -3.5 -360 0.11 6.8 195 1.7 10 -300 0.4 1 8.1 235 1.725 10.2 3.5 -240 V A ms mV V A mV mV
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FN6354.3 November 5, 2009
ISL6261A Gate Driver Timing Diagram
PWM
tPDHU tRU UGATE 1V
tFU
LGATE tFL
1V tRL tPDHL
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FN6354.3 November 5, 2009
ISL6261A Functional Pin Description
DPRSLPVR DPRSTP# CLK_EN PGOOD VR_ON
VID6
VID5
VID4 32
40 FDE PMON RBIAS VR_TT# NTC SOFT OCSET VW COMP FB 1 2 3 4 5 6 7 8 9 10 11 VDIFF
39
38
37
36
35
34
33
VID3 31 30 VID2 29 VID1 28 VID0 27 VCCP 26 LGATE 25 VSSP 24 PHASE 23 UGATE 22 BOOT 21 NC 20 VDD
3V3
GND PAD (BOTTOM)
12 VSEN
13 RTN
14 DROOP
15 DFB
16 VO
17 VSUM
18 VIN
19 VSS
FDE
Forced diode emulation enable signal. Logic high of FDE with logic low of DPRSTP# forces the ISL6261A to operate in diode emulation mode with an increased VW-COMP voltage window.
VW
A resistor from this pin to COMP programs the switching frequency (eg. 6.81k = 300kHz).
COMP
The output of the error amplifier.
PMON
Analog voltage output pin. The voltage potential on this pin indicates the power delivered to the output.
FB
The inverting input of the error amplifier.
RBIAS
A 147K resistor to VSS sets internal current reference.
VDIFF
The output of the differential amplifier.
VR_TT#
Thermal overload output indicator with open-drain output. Over-temperature pull-down resistance is 10.
VSEN
Remote core voltage sense input.
RTN
Remote core voltage sense return.
NTC
Thermistor input to VR_TT# circuit and a 60A current source is connected internally to this pin.
DROOP
The output of the droop amplifier. DROOP-VO voltage is the droop voltage.
SOFT
A capacitor from this pin to GND pin sets the maximum slew rate of the output voltage. The SOFT pin is the non-inverting input of the error amplifier.
DFB
The inverting input of the droop amplifier.
OCSET
Overcurrent set input. A resistor from this pin to VO sets DROOP voltage limit for OC trip. A 10A current source is connected internally to this pin.
VO
An input to the IC that reports the local output voltage.
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FN6354.3 November 5, 2009
ISL6261A
VSUM
This pin is connected to one terminal of the capacitor in the current sensing R-C network.
VC24CP
5V power supply for the gate driver.
VID0, VID1, VID2, VID3, VID4, VID5, VID6
VID input with VID0 as the least significant bit (LSB) and VID6 as the most significant bit (MSB).
VIN
Power stage input voltage. It is used for input voltage feed forward to improve the input line transient performance.
VR_ON
VR enable pin. A logic high signal on this pin enables the regulator.
VSS
Signal ground. Connect to controller local ground.
VDD
5V control power supply.
DPRSLPVR
Deeper sleep enable signal. A logic high indicates that the microprocessor is in Deeper Sleep Mode and also indicates a slow Vo slew rate with 41A discharging or charging the SOFT cap.
NC
Not connected. Ground this pin in the practical layout.
BOOT
Upper gate driver supply voltage. An internal bootstrap diode is connected to the VCCP pin.
DPRSTP#
Deeper sleep slow wake up signal. A logic low signal on this pin indicates that the microprocessor is in Deeper Sleep Mode.
UGATE
The upper-side MOSFET gate signal.
CLK_EN#
Digital output for system PLL clock. Goes active 13 clock cycles after Vcore is within 20mV of the boot voltage.
PHASE
The phase node. This pin should connect to the source of upper MOSFET.
3V3
3.3V supply voltage for CLK_EN#.
VSSP
The return path of the lower gate driver.
PGOOD
Power good open-drain output. Needs to be pulled up externally by a 680 resistor to VCCP or 1.9k to 3.3V.
LGATE
The lower-side MOSFET gate signal.
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FN6354.3 November 5, 2009
Function Block Diagram
RBIAS VR_ON FDE DPRSLPVR DPRSTP# CLK_EN# PGOOD 3V3 VIN VDD VCCP
VID0 VID1 VID2 VID3 VID4 VID5 VID6 10A VO 1.22V DAC SOFT MODE CONTROL PGOOD MONITOR AND LOGIC VIN 60A FLT PGOOD VCCP
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FN6354.3 November 5, 2009
FAULT AND PGOOD LOGIC
OCSET
OC
VCCP
VSUM DROOP DFB OC VIN VSOFT FLT
ISL6261A
DROOP 1 E/A MODULATOR
DRIVER LOGIC VCCP
VO
1
Mupti-plier VW
VO
VSEN
RTN
PMON
VDIFF
SOFT
FB
COMP
VW
VSS
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6261A
ISL6261A Simplified Application Circuit for DCR Current Sensing
V +3.3 R4 V +5 V in
C4
R5 R6
3V3 RBIAS NTC
VDD
VCCP VIN C8 UGATE
C5 SOFT VR_TT# VID<0:6> DPRSTP# DPRSLPVR VR_TT#
BOOT C6 PHASE L o V o C
VIDs DPRSTP# DPRSLPVR FDE LGATE VSSP
o
PMON CLK_ENABLE# VR_ON IMVP6_PWRGD VCC-SENSE VSS-SENSE R7 C7 C3 R2 C2
PMON CLK_EN# VR_ON PGOOD VSEN RTN ISL6261A
R8 VSUM C9 VO R10 R9 NTC Network
VW OCSET
R11 C10
COMP FB R3 R1 C1 VDIFF VSS
DFB R12 DROOP
FIGURE 2. ISL6261A-BASED IMVP-6(R) SOLUTION WITH INDUCTOR DCR CURRENT SENSING
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FN6354.3 November 5, 2009
ISL6261A Simplified Application Circuit for Resistive Current Sensing
V +3.3 R4 V +5 V in
C4
R5 R6
3V3 RBIAS NTC
VDD
VCCP VIN C8 UGATE
C5 SOFT VR_TT# VID<0:6> DPRSTP# DPRSLPVR VR_TT#
BOOT C6 PHASE L o R sen V o C
VIDs DPRSTP# DPRSLPVR FDE LGATE VSSP
o
PMON CLK_ENABLE# VR_ON IMVP6_PWRGD VCC-SENSE VSS-SENSE R7 C7 C3 R2 C2
PMON CLK_EN# VR_ON PGOOD VSEN RTN ISL6261A
R8 VSUM C9 VO R10
VW OCSET
R11 C10
COMP FB R3 R1 C1 VDIFF VSS
DFB R12 DROOP
FIGURE 3. ISL6261A-BASED IMVP-6(R) SOLUTION WITH RESISTIVE CURRENT SENSING
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FN6354.3 November 5, 2009
ISL6261A Theory of Operation
The ISL6261A is a single-phase regulator implementing Intel(R) IMVP-6(R) protocol and includes an integrated gate driver for reduced system cost and board area. The ISL6261A IMVP-6(R) solution provides optimum steady state and transient performance for microprocessor core voltage regulation applications up to 25A. Implementation of Diode Emulation Mode (DEM) operation further enhances system efficiency. The heart of the ISL6261A is the patented R3 TechnologyTM, Intersil's Robust Ripple Regulator modulator. The R3TM modulator combines the best features of fixed frequency and hysteretic PWM controllers while eliminating many of their shortcomings. The ISL6261A modulator internally synthesizes an analog of the inductor ripple current and uses hysteretic comparators on those signals to establish PWM pulses. Operating on the large-amplitude and noisefree synthesized signals allows the ISL6261A to achieve lower output ripple and lower phase jitter than either conventional hysteretic or fixed frequency PWM controllers. Unlike conventional hysteretic converters, the ISL6261A has an error amplifier that allows the controller to maintain 0.5% voltage regulation accuracy throughout the VID range from 0.75V to 1.5V. The hysteretic window voltage is with respect to the error amplifier output. Therefore the load current transient results in increased switching frequency, which gives the R3TM regulator a faster response than conventional fixed frequency PWM regulators.
VDD VR_ON
100s 20mV 10mV/s Vboot
SOFT &VO
2mV/s
13x s T
CLK_EN# ~7ms IMVP-VI PGOOD
FIGURE 4. SOFT-START WAVEFORMS USING A 20nF SOFT CAPACITOR
A true differential amplifier remotely senses the core voltage to precisely control the voltage at the microprocessor die. VSEN and RTN pins are the inputs to the differential amplifier. As the load current increases from zero, the output voltage droops from the VID value proportionally to achieve the IMVP-6(R) load line. The ISL6261A can sense the inductor current through the intrinsic series resistance of the inductors, as shown in Figure 2, or through a precise resistor in series with the inductor, as shown in Figure 3. The inductor current information is fed to the VSUM pin, which is the non-inverting input to the droop amplifier. The DROOP pin is the output of the droop amplifier, and DROOP-VO voltage is a high-bandwidth analog representation of the inductor current. This voltage is used as an input to a differential amplifier to achieve the IMVP-6(R) load line, and also as the input to the overcurrent protection circuit. The PMON pin is the power monitor output. The voltage potential on this pin (VPMON) is given by VPMON = 35x(VSENVRTN)x(VDROOP-VO). Since VSEN-VRTN is the CPU voltage and VDROOP-VO represents the inductor current, VPMON is an analog voltage indicating the power consumed by the CPU. VPMON has high bandwidth so it represents the instantaneous power including the pulsation caused inductor current switching ripple. The maximum available VPMON is approximately 3V. When using inductor DCR current sensing, an NTC thermistor is used to compensate the positive temperature coefficient of the copper winding resistance to maintain the load-line accuracy. The switching frequency of the ISL6261A controller is set by the resistor RFSET between pins VW and COMP, as shown in Figures 2 and 3.
Start-up Timing
With the controller's VDD pin voltage above the POR threshold, the start-up sequence begins when VR_ON exceeds the 3.3V logic HIGH threshold. In approximately 100s, SOFT and VO start ramping to the boot voltage of 1.2V. At start-up, the regulator always operates in Continuous Current Mode (CCM), regardless of the control signals. During this interval, the SOFT cap is charged by a 41A current source. If the SOFT capacitor is 20nF, the SOFT ramp will be 2mV/s for a soft-start time of 600s. Once VO is within 20mV of the boot voltage the ISL6261A will count 13 clock cycles, then pull CLK_EN# low, and charge/discharge the SOFT cap with approximately 200A, therefore VO slews at 10mV/s to the voltage set by the VID pins. In approximately 7ms, PGOOD is asserted HIGH. Figure 4 shows typical start-up timing.
Static Operation
After the start-up sequence, the output voltage will be regulated to the value set by the VID inputs per Table 1, which is presented in the lntel(R) IMVP-6(R) specification. The ISL6261A regulates the output voltage with 0.5% accuracy over the range of 0.7V to 1.5V.
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ISL6261A
TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VO (V) 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION (Continued) VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 VID3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 VID2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VO (V) 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625
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TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION (Continued) VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VO (V) 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION (Continued) VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VO (V) 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000
TABLE 2. ISL6261A OPERATING CONFIGURATIONS DPRSTP# 0 x <3 consecutive PWM with PHASE>0V 1 PHASE DETECTOR HISTORY FDE 0 DPRSLPVR 0 1 0 1 Three consecutive PWM with PHASE>0V 0 1 1 0 1 1 x x x CCM 0% EDEM +40% OPERATIONAL MODE CCM DEM +20% VW-COMP VOLTAGE WINDOW INCREASE 0%
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High Efficiency Operation Mode
The operational modes of the ISL6261A depend on the control signal states of DPRSTP#, FDE, and DPRSLPVR, as shown in Table 2. These control signals can be tied to lntel(R) IMVP-6(R) control signals to maintain the optimal system configuration for all IMVP-6(R) conditions. DPRSTP# = 0, FDE = 0 and DPRSLPVR = 1 enables the ISL6261A to operate in Diode Emulation Mode (DEM) by monitoring the low-side FET current. In diode emulation mode, when the low-side FET current flows from source to drain, it turns on as a synchronous FET to reduce the conduction loss. When the current reverses its direction, trying to flow from drain to source, the ISL6261A turns off the low-side FET to prevent the output capacitor from discharging through the inductor, therefore eliminating the extra conduction loss. When DEM is enabled, the regulator works in automatic Discontinuous Conduction Mode (DCM), meaning that the regulator operates in CCM in heavy load, and operates in DCM in light load. DCM in light load decreases the switching frequency to increase efficiency. This mode can be used to support the deeper sleep mode of the microprocessor. DPRSTP# = 0 and FDE = 1 enables the Enhanced Diode Emulation Mode (EDEM), which increases the VW-COMP window voltage by 33%. This further decreases the switching frequency at light load to boost efficiency in the deeper sleep mode. For other combinations of DPRSTP#, FDE, and DPRSLPVR, the ISL6261A operates in forced CCM. The ISL6261A operational modes can be set according to CPU mode signals to achieve the best performance. There are two options: (1) Tie FDE to DPRSLPVR, and tie DPRSTP# and DPRSLPVR to the corresponding CPU mode signals. This configuration enables EDEM in deeper sleep mode to increase efficiency. (2) Tie FDE to "1" and DPRSTP# to "0" permanently, and tie DPRSLPVR to the corresponding CPU mode signal. This configuration sets the regulator in EDEM all the time. The regulator will enter DCM based on load current. Light-load efficiency is increased in both active mode and deeper sleep mode. CPU mode-transition sequences often occur in concert with VID changes. The ISL6261A employs carefully designed mode-transition timing to work in concert with the VID changes. The ISL6261A is equipped with internal counters to prevent control signal glitches from triggering unintended mode transitions. For example: Control signals lasting less than seven switching periods will not enable the diode emulation mode.
Dynamic Operation
The ISL6261A responds to VID changes by slewing to new voltages with a dv/dt set by the SOFT capacitor and the logic of DPRSLPVR. If CSOFT = 20nF and DPRSLPVR = 0, the output voltage will move at a maximum dv/dt of 10mV/s for large changes. The maximum dv/dt can be used to achieve fast recovery from Deeper Sleep to Active mode. If CSOFT = 20nF and DPRSLPVR = 1, the output voltage will move at a dv/dt of 2mV/s for large changes. The slow dv/dt into and out of deeper sleep mode will minimize the audible noise. As the output voltage approaches the VID command value, the dv/dt moderates to prevent overshoot. The ISL6261A is IMVP-6(R) compliant for DPRSTP# and DPRSLPVR logic. Intersil R3TM has an intrinsic voltage feed forward function. High-speed input voltage transients have little effect on the output voltage. Intersil R3TM commands variable switching frequency during transients to achieve fast response. Upon load application, the ISL6261A will transiently increase the switching frequency to deliver energy to the output more quickly. Compared with steady state operation, the PWM pulses during load application are generated earlier, which effectively increases the duty cycle and the response speed of the regulator. Upon load release, the ISL6261A will transiently decrease the switching frequency to effectively reduce the duty cycle to achieve fast response.
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6261A FAULT TYPE Overcurrent fault Way-Overcurrent fault Overvoltage fault (1.7V) FAULT DURATION PRIOR TO PROTECTION 120s <2s Immediately PROTECTION ACTIONS PWM tri-state, PGOOD latched low PWM tri-state, PGOOD latched low Low-side FET on until Vcore < 0.85V, then PWM tri-state, PGOOD latched low (OV-1.7V always) PWM tri-state, PGOOD latched low PWM tri-state, PGOOD latched low VR_TT# goes high FAULT RESET VR_ON toggle or VDD toggle VR_ON toggle or VDD toggle VDD toggle
Overvoltage fault (+200mV) Undervoltage fault (-300mV)
1ms 1ms
VR_ON toggle or VDD toggle VR_ON toggle or VDD toggle N/A
Over-temperature fault (NTC<1.18) Immediately
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Protection
The ISL6261A provides overcurrent (OC), overvoltage (OV), undervoltage (UV) and over-temperature (OT) protections as shown in Table 3. Overcurrent is detected through the droop voltage, which is designed as described in the "Component Selection and Application" section. The OCSET resistor sets the overcurrent protection level. An overcurrent fault will be declared when the droop voltage exceeds the overcurrent set point for more than 120s. A way-overcurrent fault will be declared in less than 2s when the droop voltage exceeds twice the overcurrent set point. In both cases, the UGATE and LGATE outputs will be tri-stated and PGOOD will go low. The overcurrent condition is detected through the droop voltage. The droop voltage is equal to Icore x Rdroop, where Rdroop is the load line slope. A 10A current source flows out of the OCSET pin and creates a voltage drop across ROCSET (shown as R10 in Figure 2). Overcurrent is detected when the droop voltage exceeds the voltage across ROCSET. Equation 1 gives the selection of ROCSET. The ISL6261A has a thermal throttling feature. If the voltage on the NTC pin goes below the 1.2V over-temperature threshold, the VR_TT# pin is pulled low indicating the need for thermal throttling to the system oversight processor. No other action is taken within the ISL6261A.
Component Selection and Application
Soft-Start and Mode Change Slew Rates
The ISL6261A commands two different output voltage slew rates for various modes of operation. The slow slew rate reduces the inrush current during start-up and the audible noise during the entry and the exit of Deeper Sleep Mode. The fast slew rate enhances the system performance by achieving active mode regulation quickly during the exit of Deeper Sleep Mode. The SOFT current is bidirectional-charging the SOFT capacitor when the output voltage is commanded to rise, and discharging the SOFT capacitor when the output voltage is commanded to fall. Figure 5 shows the circuitry on the SOFT pin. The SOFT pin, the non-inverting input of the error amplifier, is connected to ground through capacitor CSOFT. ISS is an internal current source connected to the SOFT pin to charge or discharge CSOFT. The ISL6261A controls the output voltage slew rate by connecting or disconnecting another internal current source IZ to the SOFT pin, depending on the state of the system, i.e. Start-up or Active mode, and the logic state on the DPRSLPVR pin. The SOFT-START CURRENT section of the Electrical Specification Table shows the specs of these two current sources.
ROCSET =
I OC x Rdroop 10 A
(EQ. 1)
For example: The desired overcurrent trip level, Ioc, is 30A, Rdroop is 2.1m, Equation 1 gives ROCSET = 6.3k. Undervoltage protection is independent of the overcurrent limit. A UV fault is declared when the output voltage is lower than (VID-300mV) for more than 1ms. The gate driver outputs will be tri-stated and PGOOD will go low. Note that a practical core regulator design usually trips OC before it trips UV. There are two levels of overvoltage protection and response. An OV fault is declared when the output voltage exceeds the VID by +200mV for more than 1ms. The gate driver outputs will be tri-stated and PGOOD will go low. The inductor current will decay through the low-side FET body diode. Toggling of VR_ON or bringing VDD below 4V will reset the fault latch. A way-overvoltage (WOV) fault is declared immediately when the output voltage exceeds 1.7V. The ISL6261A will latch PGOOD low and turn on the low-side FETs. The low-side FETs will remain on until the output voltage drops below approximately 0.85V, then all the FETs are turned off. If the output voltage again rises above 1.7V, the protection process repeats. This mechanism provides maximum protection against a shorted high-side FET while preventing the output from ringing below ground. Toggling VR_ON cannot reset the WOV protection; recycling VDD will reset it. The WOV detector is active all the time, even when other faults are declared, so the processor is still protected against the high-side FET leakage while the FETs are commanded off.
I SS
I Z INTERNAL TO ISL6261A
ERROR AMPLIFLIER
C SOFT
V REF
FIGURE 5. SOFT PIN CURRENT SOURCES FOR FAST AND SLOW SLEW RATES
ISS is 41A typical and is used during start-up and mode changes. When connected to the SOFT pin, IZ adds to ISS to get a larger current, labeled IGV in the "Electrical Specification Table" starting on page 3, on the SOFT pin. IGV is typically 200A with a minimum of 175A.
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10A OCSET OC R ocset I phase L
DCR
Vo
VSUM INTERNAL TO ISL6261A DROOP series DFB
Rs C o
ESR
DROOP R drp2 1 VO Cn R R opn1 R ntc par
1000pF VSEN 1 RTN 1000pF
R drp1
0~10
R
VCC-SENSE
TO PROCESSOR SOCKET KELVIN CONECTIONS
VSS-SENSE 330pF opn2
VDIFF
FIGURE 6. SIMPLIFIED VOLTAGE DROOP CIRCUIT WITH CPU-DIE VOLTAGE SENSING AND INDUCTOR DCR CURRENT SENSING
The IMVP-6(R) specification reveals the critical timing associated with regulating the output voltage. SLEWRATE, given in the IMVP-6(R) specification, determines the choice of the SOFT capacitor, CSOFT, through Equation 2:
Start-up Operation - CLK_EN# and PGOOD
The ISL6261A provides a 3.3V logic output pin for CLK_EN#. The system 3.3V voltage source connects to the 3V3 pin, which powers internal circuitry that is solely devoted to the CLK_EN# function. The output is a CMOS signal with 4mA sourcing and sinking capability. CMOS logic eliminates the need for an external pull-up resistor on this pin, eliminating the loss on the pull-up resistor caused by CLK_EN# being low in normal operation. This prolongs battery run time. The 3.3V supply should be decoupled to digital ground, not to analog ground, for noise immunity. At start-up, CLK_EN# remains high until 13 clock cycles after the core voltage is within 20mV of the boot voltage. The ISL6261A triggers an internal timer for the IMVP6_PWRGD signal (PGOOD pin). This timer allows PGOOD to go high approximately 7ms after CLK_EN# goes low.
CSOFT =
I GV SLEWRATE
(EQ. 2)
If SLEWRATE is 10mV/s, and IGV is typically 200A, CSOFT is calculated as:
C SOFT = 200 A (10 mV s ) = 20 nF
(EQ. 3)
Choosing 0.015F will guarantee 10mV/s SLEWRATE at minimum IGV value. This choice of CSOFT controls the startup slew rate as well. One should expect the output voltage to slew to the Boot value of 1.2V at a rate given by Equation 4:
dV soft dt
=
I ss C SOFT
=
41A = 2.8 mV s 0.015 F
(EQ. 4)
Selecting Rbias
To properly bias the ISL6261A, a reference current needs to be derived by connecting a 147k, 1% tolerance resistor from the RBIAS pin to ground. This provides a very accurate 10A current source from which OCSET reference current is derived. Caution should be used during layout. This resistor should be placed in close proximity to the RBIAS pin and be connected to good quality signal ground. Do not connect any other components to this pin, as they will negatively impact the performance. Capacitance on this pin may create instabilities and should be avoided.
Static Mode of Operation - Processor Die Sensing
Remote sensing enables the ISL6261A to regulate the core voltage at a remote sensing point, which compensates for various resistive voltage drops in the power delivery path. The VSEN and RTN pins of the ISL6261A are connected to Kelvin sense leads at the die of the processor through the processor socket. (The signal names are Vcc_sense and Vss_sense respectively). Processor die sensing allows the voltage regulator to tightly control the processor voltage at the die, free of the inconsistencies and the voltage drops due to layouts. The Kelvin sense technique provides for extremely tight load line regulation at the processor die side.
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These traces should be laid out as noise sensitive traces. For optimum load line regulation performance, the traces connecting these two pins to the Kelvin sense leads of the processor should be laid out away from rapidly rising voltage nodes (switching nodes) and other noisy traces. Common mode and differential mode filters are recommended as shown in Figure 6. The recommended filter resistance range is 0~10 so it does not interact with the 50k input resistance of the differential amplifier. The filter resistor may be inserted between VCC-SENSE and the VSEN pin. Another option is to place one between VCC-SENSE and the VSEN pin and another between VSS-SENSE and the RTN pin. The need of these filters also depends on the actual board layout and the noise environment. Since the voltage feedback is sensed at the processor die, if the CPU is not installed, the regulator will drive the output voltage all the way up to damage the output capacitors due to lack of output voltage feedback. Ropn1 and Ropn2 are recommended, as shown in Figure 6, to prevent this potential issue. Ropn1 and Ropn2, typically ranging 20~100, provide voltage feedback from the regulator local output in the absence of the CPU.
54A
6A
Internal to ISL6261A VR_TT#
NTC
SW1
V
NTC
R
NTC SW2
R
S
1.23V
1.20V
FIGURE 7. CIRCUITRY ASSOCIATED WITH THE THERMAL THROTTLING FEATURE
Setting the Switching Frequency - FSET
The R3 modulator scheme is not a fixed frequency PWM architecture. The switching frequency increases during the application of a load to improve transient performance. It also varies slightly depending on the input and output voltages and output current, but this variation is normally less than 10% in continuous conduction mode. Resistor Rfset (R7 in Figure 2), connected between the VW and COMP pins of the ISL6261A, sets the synthetic ripple window voltage, and therefore sets the switching frequency. This relationship between the resistance and the switching frequency in CCM is approximately given by Equation 5.
R fset (k ) = ( period(s) - 0.29) x 2.33
(EQ. 5)
Figure 7 shows the circuitry associated with the thermal throttling feature of the ISL6261A. At low temperature, SW1 is on and SW2 connects to the 1.20V side. The total current going into the NTC pin is 60A. The voltage on the NTC pin is higher than 1.20V threshold voltage and the comparator output is low. VR_TT# is pulled up high by an external resistor. Temperature increase will decrease the NTC thermistor resistance. This decreases the NTC pin voltage. When the NTC pin voltage drops below 1.2V, the comparator output goes high to pull VR_TT# low, signaling a thermal throttle. In addition, SW1 turns off and SW2 connects to 1.23V, which decreases the NTC pin current by 6uA and increases the threshold voltage by 30mV. The VR_TT# signal can be used by the system to change the CPU operation and decrease the power consumption. As the temperature drops, the NTC pin voltage goes up. If the NTC pin voltage exceeds 1.23V, VR_TT# will be pulled high. Figure 8 illustrates the temperature hysteresis feature of VR_TT#. T1 and T2 (T1>T2) are two threshold temperatures. VR_TT# goes low when the temperature is higher than T1 and goes high when the temperature is lower than T2.
In diode emulation mode, the ISL6261A stretches the switching period. The switching frequency decreases as the load becomes lighter. Diode emulation mode reduces the switching loss at light load, which is important in conserving battery power.
VR_TT# Logic_1
Voltage Regulator Thermal Throttling
lntel(R) IMVP-6(R) technology supports thermal throttling of the processor to prevent catastrophic thermal damage to the voltage regulator. The ISL6261A features a thermal monitor sensing the voltage across an externally placed negative temperature coefficient (NTC) thermistor. Proper selection and placement of the NTC thermistor allows for detection of a designated temperature rise by the system.
Logic_0 T2 T1 T (oC)
FIGURE 8. VR_TT# TEMPERATURE HYSTERISIS
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The NTC thermistor's resistance is approximately given by the following formula: Once RNTCTo and Rs is designed, the actual NTC resistance at T2 and the actual T2 temperature can be found in:
R
NTC
(T ) = R
NTCTo
1 1 b( - ) T + 273 To + 273 e
(EQ. 6)
RNTC _ T 2 = 2.78k + RNTC _ T 1
T2 _ actual = 1 1 R NTC _ T2 ln( ) + 1 ( 273 + To ) b R NTCTo - 273
(EQ. 13)
T is the temperature of the NTC thermistor and b is a constant determined by the thermistor material. To is the reference temperature at which the approximation is derived. The most commonly used To is +25C. For most commercial NTC thermistors, there is b = 2750k, 2600k, 4500k or 4250k. From the operation principle of VR_TT#, the NTC resistor satisfies the following equation group:
(EQ. 14)
One example of using Equations 10, 11 and 12 to design a thermal throttling circuit with the temperature hysteresis +100C to +105C is illustrated as follows. Since T1 = +105C and T2 = +100C, if we use a Panasonic NTC with b = 4700, Equation 9 gives the required NTC nominal resistance as
R NTC (T1 ) + Rs =
R NTC (T2 ) + Rs =
1.20V = 20k 60 A
1.23V = 22.78k 54 A
(EQ. 7)
R NTC_To = 431k
The NTC thermistor datasheet gives the resistance ratio as 0.03956 at +100C and 0.03322 at +105C. The b value of 4700k in Panasonic datasheet only covers up to +85C; therefore, using Equation 11 is more accurate for +100C design and the required NTC nominal resistance at +25C is 438k. The closest NTC resistor value from manufacturers is 470k. So Equation 12 gives the series resistance as follows:
(EQ. 8)
From Equation 7 and Equation 8, the following can be derived:
RNTC(T2 ) - RNTC(T1 ) = 2.78k
(EQ. 9)
Substitution of Equation 6 into Equation 9 yields the required nominal NTC resistor value:
Rs = 20k - R NTC _ 105C = 20k - 15.61k = 4.39k
The closest standard value is 4.42k. Furthermore, Equation 13 gives the NTC resistance at T2:
RNTCTo = e
2.78k e
1 b( ) T2 + 273
b(
1 ) To + 273
(EQ. 10)
-e
1 b( ) T1 + 273
RNTC _ T 2 = 2.78k + RNTC _ T 1 = 18.39k
The NTC branch is designed to have a 470k NTC and a 4.42k resistor in series. The part number of the NTC thermistor is ERTJ0EV474J. It is a 0402 package. The NTC thermistor should be placed in the spot that gives the best indication of the temperature of the voltage regulator. The actual temperature hysteretic window is approximately +105C to +100C.
In some cases, the constant b is not accurate enough to approximate the resistor value; manufacturers provide the resistor ratio information at different temperatures. The nominal NTC resistor value may be expressed in another way as follows:
RNTCTo =
2.78k R NTC (T2 ) - R NTC (T1 )

(EQ. 11)
where R NTC (T ) is the normalized NTC resistance to its nominal value. The normalized resistor value on most NTC thermistor datasheets is based on the value at +25C. Once the NTC thermistor resistor is determined, the series resistor can be derived by:
Rs =
1.20V - R NTC (T1 ) = 20k - R NTC_T1 60 A
(EQ. 12)
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10A OCSET OC R ocset VO
VSUM Internal to ISL6261A DROOP
Rs
DFB I o
DROOP Cn 1 R drp2 R par
R series
Vdcr
DCR
VO
R ntc Rn
(Rntc +Rseries )
Rpar
FIGURE 9. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DCR SENSING
Static Mode of Operation - Static Droop Using DCR Sensing
The ISL6261A has an internal differential amplifier to accurately regulate the voltage at the processor die. For DCR sensing, the process to compensate the DCR resistance variation takes several iterative steps. Figure 2 shows the DCR sensing method. Figure 9 shows the simplified model of the droop circuitry. The inductor DC current generates a DC voltage drop on the inductor DCR. Equation 15 gives this relationship.
R drp1
Rntc +Rseries +Rpar
G1, the gain of Vn to VDCR, is also dependent on the temperature of the NTC thermistor:
G1 (T ) =
Rn (T ) Rn (T ) + Rs
(EQ. 17)
The inductor DCR is a function of the temperature and is approximately given by Equation 18:
DCR(T ) = DCR25C (1 + 0.00393 * (T - 25))
(EQ. 18)
V DCR = I o x DCR
(EQ. 15)
in which 0.00393 is the temperature coefficient of the copper. The droop amplifier output voltage divided by the total load current is given by Equation 19:
An R-C network senses the voltage across the inductor to get the inductor current information. Rn represents the NTC network consisting of Rntc, Rseries and Rpar. The choice of Rs will be discussed in the next section. The first step in droop load line compensation is to choose Rn and Rs such that the correct droop voltage appears even at light loads between the VSUM and VO nodes. As a rule of thumb, the voltage drop across the Rn network, Vn, is set to be 0.5 to 0.8 times VDCR. This gain, defined as G1, provides a fairly reasonable amount of light load signal from which to derive the droop voltage. The NTC network resistor value is dependent on the temperature and is given by Equation 16:
Rdroop = G1(T) DCR (T ) k droopamp
(EQ. 19)
Rdroop is the actual load line slope. To make Rdroop independent of the inductor temperature, it is desired to have:
G1 (T ) (1 + 0.00393 * (T - 25)) G1t arg et
(EQ. 20)
where G1target is the desired ratio of Vn/VDCR. Therefore, the temperature characteristics G1 is described by Equation 21:
G 1 (T ) =
G 1 t arg et (1 + 0.00393* (T - 25)
(EQ. 21)
Rn (T ) =
( Rseries + Rntc ) R par Rseries + Rntc + R par
(EQ. 16)
For different G1 and NTC thermistor preference, Intersil provides a design spreadsheet to generate the proper value of Rntc, Rseries, Rpar. Rdrp1 (R11 in Fig. 2) and Rdrp2 (R12 in Figure 2) sets the droop amplifier gain, according to Equation 22:
k droopamp = 1 +
Rdrp 2 R drp1
(EQ. 22)
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After determining Rs and Rn networks, use Equation 23 to calculate the droop resistances Rdrp1 and Rdrp2. response. Figure 11 shows the transient response when Cn is too small. Vcore may sag excessively upon load application to create a system failure. Figure 12 shows the transient response when Cn is too large. Vcore is sluggish in drooping to its final value. There will be excessive overshoot if a load occurs during this time, which may potentially hurt the CPU reliability.
Rdrp 2 = (
Rdroop DCR G1(25 o C )
- 1) Rdrp1
(EQ. 23)
Rdroop is 2.1mV/A per lntel(R) IMVP-6(R) specification. The effectiveness of the Rn network is sensitive to the coupling coefficient between the NTC thermistor and the inductor. The NTC thermistor should be placed in close proximity of the inductor. To verify whether the NTC network successfully compensates the DCR change over temperature, one can apply full load current, wait for the thermal steady state, and see how much the output voltage deviates from the initial voltage reading. Good thermal compensation can limit the drift to less than 2mV. If the output voltage decreases when the temperature increases, that ratio between the NTC thermistor value and the rest of the resistor divider network has to be increased. Following the evaluation board value and layout of NTC placement will minimize the engineering time. The current sensing traces should be routed directly to the inductor pads for accurate DCR voltage drop measurement. However, due to layout imperfection, the calculated Rdrp2 may still need slight adjustment to achieve optimum load line slope. It is recommended to adjust Rdrp2 after the system has achieved thermal equilibrium at full load. For example, if the max current is 20A, one should apply 20A load current and look for 42mV output voltage droop. If the voltage droop is 40mV, the new value of Rdpr2 is calculated by:
icore Vcore
Icore Vcore
Vcore
Vcore= IcorexRdroop FIGURE 10. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
icore Vcore
Vcore
FIGURE 11. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO SMALL
icore Vcore
R drp 2 _ new =
42 mV ( R drp 1 + R drp 2 ) - R drp 1 40 mV
Vcore
(EQ. 24)
For the best accuracy, the effective resistance on the DFB and VSUM pins should be identical so that the bias current of the droop amplifier does not cause an offset voltage. The effective resistance on the VSUM pin is the parallel of Rs and Rn, and the effective resistance on the DFB pin is the parallel of Rdrp1 and Rdrp2.
FIGURE 12. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO LARGE
Dynamic Mode of Operation - Droop Capacitor Design in DCR Sensing
Figure 10 shows the desired waveforms during load transient response. Vcore needs to be as square as possible at Icore change. The Vcore response is determined by several factors, namely the choice of output inductor and output capacitor, the compensator design, and the droop capacitor design. The droop capacitor refers to Cn in Figure 9. If Cn is designed correctly, its voltage will be a high-bandwidth analog voltage of the inductor current. If Cn is not designed correctly, its voltage will be distorted from the actual waveform of the inductor current and worsen the transient
The current sensing network consists of Rn, Rs and Cn. The effective resistance is the parallel of Rn and Rs. The RC time constant of the current sensing network needs to match the L/DCR time constant of the inductor to get correct representation of the inductor current waveform. Equation 25 shows this equation:
R x Rs L x Cn = n DCR Rn + Rs
Solving for Cn yields:
(EQ. 25)
L C n = DCR Rn x Rs Rn + Rs
(EQ. 26)
21
FN6354.3 November 5, 2009
ISL6261A
For example: L = 0.45H, DCR = 1.1m, Rs = 7.68k, and Rn = 3.4k in the FB pin. It is recommended to keep this resistor below 3k.
0.45H 0.0011 Cn = = 174nF parallel(7.68k ,3.4k )
(EQ. 27)
Droop using Discrete Resistor Sensing Static/Dynamic Mode of Operation
Figure 3 shows a detailed schematic using discrete resistor sensing of the inductor current. Figure 14 shows the equivalent circuit. Since the current sensing resistor voltage represents the actual inductor current information, Rs and Cn simply provide noise filtering. The most significant noise comes from the ESL of the current sensing resistor. A low low ESL sensing resistor is strongly recommended. The recommended Rs is 100 and the recommended Cn is 220pF. Since the current sensing resistance does not appreciably change with temperature, the NTC network is not needed for thermal compensation. Droop is designed the same way as the DCR sensing approach. The voltage on the current sensing resistor is given by the following Equation 28:
Since the inductance and the DCR typically have 20% and 7% tolerance respectively, the L/DCR time constant of each individual inductor may not perfectly match the RC time constant of the current sensing network. In mass production, this effect will make the transient response vary a little bit from board to board. Compared with potential long-term damage on CPU reliability, an immediate system failure is worse. So it is desirable to avoid the waveforms shown in Figure 11. It is recommended to choose the minimum Cn value based on the maximum inductance so only the scenarios of Figures 10 and 12 may happen. It should be noted that, after calculation, fine-tuning of Cn value may still be needed to account for board parasitics. Cn also needs to be a high-grade cap like X7R with low tolerance. Another good option is the NPO/COG (class-I) capacitor, featuring only 5% tolerance and very good thermal characteristics. But the NPO/COG caps are only available in small capacitance values. In order to use such capacitors, the resistors and thermistors surrounding the droop voltage sensing and droop amplifier need to be scaled up 10X to reduce the capacitance by 10X. Attention needs to be paid in balancing the impedance of droop amplifier.
Vrsen = Rsen I o
(EQ. 28)
Equation 21 shows the droop amplifier gain. So the actual droop is given by Equation 29:
Rdrp 2 Rdroop = Rsen 1 + R drp1
Solving for Rdrp2 yields:
(EQ. 29)
Dynamic Mode of Operation - Compensation Parameters
The voltage regulator is equivalent to a voltage source equal to VID in series with the output impedance. The output impedance needs to be 2.1m in order to achieve the 2.1mV/A load line. It is highly recommended to design the compensation such that the regulator output impedance is 2.1m. A type-III compensator is recommended to achieve the best performance. Intersil provides a spreadsheet to design the compensator parameters. Figure 13 shows an example of the spreadsheet. After the user inputs the parameters in the blue font, the spreadsheet will calculate the recommended compensator parameters (in the pink font), and show the loop gain curves and the regulator output impedance curve. The loop gain curves need to be stable for regulator stability, and the impedance curve needs to be equal to or smaller than 2.1m in the entire frequency range to achieve good transient response. The user can choose the actual resistor and capacitor values based on the recommendation and input them in the spreadsheet, then see the actual loop gain curves and the regulator output impedance curve. Caution needs to be used in choosing the input resistor to the FB pin. Excessively high resistance will cause an error to the output voltage regulation due to the bias current flowing
Rdroop Rdrp 2 = Rdrp1 R - 1 sen
(EQ. 30)
For example: Rdroop = 2.1m. If Rsen = 1m and Rdrp1 = 1k, easy calculation gives that Rdrp2 is 1.1k. The current sensing traces should be routed directly to the current sensing resistor pads for accurate measurement. However, due to layout imperfections, the calculated Rdrp2 may still need slight adjustment to achieve optimum load line slope. It is recommended to adjust Rdrp2 after the system has achieved thermal equilibrium at full load.
22
FN6354.3 November 5, 2009
ISL6261A
FIGURE 13. AN EXAMPLE OF ISL6261A COMPENSATION SPREADSHEET
23
VSS
FN6354.3 November 5, 2009
ISL6261A
10A OCSET OC Rocset VO
VSUM Internal to ISL6261A DROOP
Rs
DFB I o
DROOP R drp2 1 Cn
Vrsen
Rsen
VO
FIGURE 14. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DISCRETE RESISTOR SENSING
Typical Performance (ISL6261 Data, Taken on ISL6261A Eval1 Rev.A Evaluation Board)
R drp1
FIGURE 15. CCM EFFICIENCY, VID = 1.1V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 16. CCM LOAD LINE AND THE SPEC, VID = 1.1V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 17. DEM EFFICIENCY, VID = 0.7625V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 18. DEM LOAD LINE AND THE SPEC, VID = 0.7625V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
24
FN6354.3 November 5, 2009
ISL6261A Typical Performance (ISL6261 Data, Taken on ISL6261A Eval1 Rev.A Evaluation Board) (Continued)
FIGURE 19. ENHANCED DEM EFFICIENCY, VID = 0.7625V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 20. ENHANCED DEM LOAD LINE, VID = 0.7625V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 21. ENHANCED DEM EFFICIENCY, VID = 1.1V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 22. ENHANCED DEM LOAD LINE, VID = 1.1V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
5V/div
5V/div
0.5V/div
0.5V/div
1V/div 10V/div
FIGURE 23. SOFT-START, VIN = 19V, Io = 0A, VID = 1.5V, Ch1: VR_ON, Ch2: VO, Ch3: PMON, Ch4: PHASE
1V/div 10V/div
FIGURE 24. SOFT-START, VIN = 19V, Io = 0A, VID = 1.1V, Ch1: VR_ON, Ch2: VO, Ch3: PMON, Ch4: PHASE
25
FN6354.3 November 5, 2009
ISL6261A Typical Performance (ISL6261 Data, Taken on ISL6261A Eval1 Rev.A Evaluation Board) (Continued)
5V/div
5V/div
0.1V/div
0.1V/div
1V/div 10V/div
FIGURE 25. VBOOT TO VID, VIN = 19V, Io = 2A, VID = 1.5V, Ch1: CLK_EN#, Ch2: VO, Ch3: PMON, Ch4: PHASE
1V/div 10V/div
FIGURE 26. VBOOT TO VID, VIN = 19V, Io = 2A, VID = 0.7625V, Ch1: CLK_EN#, Ch2: VO, Ch3: PMON, Ch4: PHASE
5V/div 0.5V/div 7.68ms 5V/div
10V/div
FIGURE 27. CLK_EN AND PGOOD ASSERTION DELAY, VIN = 19V, Io = 2A, VID = 1.1V, Ch1: CLK_EN#, Ch2: VO, Ch3: PGOOD, Ch4: PHASE FIGURE 28. SHUT DOWN, VIN = 12.6V, Io = 2A, VID = 1.1V, Ch1: VR_ON, Ch2: VO, Ch3: PGOOD, Ch4: PHASE
FIGURE 29. SOFT START INRUSH CURRENT, VIN = 19V, Io = 2A, VID = 1.1V, Ch1: DROOP-VO (2.1mV = 1A), Ch2: VO, Ch3: Vcomp, Ch4: PHASE
FIGURE 30. VIN TRANSIENT TEST, VIN = 8 19V, Io = 2A, VID = 1.1V, Ch2: VO, Ch3: VIN, Ch4: PHASE
26
FN6354.3 November 5, 2009
ISL6261A Typical Performance (ISL6261 Data, Taken on ISL6261A Eval1 Rev.A Evaluation Board) (Continued)
FIGURE 31. C4 ENTRY/EXIT, VIN = 12.6V, Io = 0.7A, HFM/LFM/C4 VID = 1.05V/0.8375V/0.7625V, FDE = DPRSLPVR, Ch1: PMON, Ch2: VO, Ch3: 40k/100pF FILTERED PMON, Ch4: PHASE
FIGURE 32. VID TOGGLING, VIN = 12.6V, Io= 16.5A, HFM/LFM VID = 1.05V/0.8375V, FDE = DPRSLPVR, Ch1: PMON, Ch2: VO, Ch3: 40k/100pF FILTERED PMON, Ch4: PHASE
FIGURE 33. LOAD TRANSIENT RESPONSE IN CCM VIN = 12.6V, Io = 2A 20A (100A/s), VID = 1.1V, Ch1: PMON, Ch2: VO, Ch3: 40k/100pF FILTERED PMON, Ch4: PHASE
FIGURE 34. LOAD TRANSIENT RESPONSE IN CCM VIN = 12.6V, Io = 20A 2A (50A/s), VID = 1.1V, Ch1: PMON, Ch2: VO, Ch3: 40k/100pF FILTERED PMON, Ch4: PHASE
100A/us
50A/us
FIGURE 35. LOAD TRANSIENT RESPONSE IN CCM VIN = 12.6V, Io = 2A 20A (100A/s) 2A (50A/s), VID = 1.1V, Ch1: PMON, Ch2: VO, Ch3: 40k/100pF FILTERED PMON, Ch4: PHASE
FIGURE 36. LOAD TRANSIENT RESPONSE IN EDEM VIN = 8V, Io = 2A 20A, VID = 1.1V, Ch1: Io, Ch2: VO, Ch3: PMON, Ch4: PHASE
27
FN6354.3 November 5, 2009
ISL6261A Typical Performance (ISL6261 Data, Taken on ISL6261A Eval1 Rev.A Evaluation Board) (Continued)
100A/us
50A/us
FIGURE 37. LOAD TRANSIENT RESPONSE IN EDEM VIN = 8V, Io = 2A 20A, VID = 1.1V, Ch1: Io, Ch2: VO, Ch3: PMON, Ch4: PHASE
FIGURE 38. LOAD TRANSIENT RESPONSE IN EDEM VIN = 8V, Io = 2A 20A, VID = 1.1V, Ch1: Io, Ch2: VO, Ch3: PMON, Ch4: PHASE
120us
FIGURE 39. OVERCURRENT PROTECTION, VIN = 12.6V, Io = 0A 28A, VID = 1.1V, Ch1: DROOP-VO (2.1mV = 1A), Ch2: VO, Ch3: PGOOD, Ch4: PHASE
FIGURE 40. OVERVOLTAGE (>1.7V) PROTECTION, VIN = 12.6V, Io = 2A, VID = 1.1V, Ch2: VO, Ch3: PGOOD, Ch4: PHASE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 28
FN6354.3 November 5, 2009
ISL6261A Eval1 Evaluation Board Schematics
Controller
P13 P16 P18 P19 P20 P23 P24 P25 P27 P28
+3.3V1
J8 1 12 2 2
3 4 5
S1 1 2 3 4 5 ON ON ON ON ON
10 9 8 7 6
R108
C92
DNP
SD05H0SK
R103
10K R10
10K R14
10K R18
10K R21
3 R2 510 J9 1 12 2 1
10K
+3.3V
DNP DPRSTP# FDE
DPRSLPVR PSI# PMON/PGD_IN
P33
P31
+3.3V
P2
10K R36
10K R37
10K R38
10K R40
10K R41
10K R42
10K
IN IN IN
R32
R107 0
U1
1 2 3 4 5 6 7
OUT
VR_ON DPRSLPVR DPRSTP# CLK_EN#
J15 1 12 2 J10
IN IN IN IN IN IN IN
R1 510
SSL_LXA3025IGC
FDE +3.3V PSI#
D3
PGOOD
11 22 33
GRN
RED
1UF
1X3
3V3
2 21
J17
J1
+3.3V PGOOD DPRSLPVR
1 2 3 4 5 6 7
14 13 12 11 10 9 8 MST7_SPST
P6
10K
R3
OUT
C24
VID6 VID5 VID4 VID3 VID2 VID1 VID0
1
5V
R47
14 13 12 11 10 9 8
3.3V
100
P10
R17 DNP R16
P14
P7
P1
DNP
PGOOD 3V3 CLK_EN DPRSTP DPRSLPVR VR_ON VID6 VID5 VID4 VID3
R46
34 2
0.015UF C10
147K
R20
P34
DNP
C17
Q5
C8
1
499
R22
2N7002
10UF
R39
C30
2
+3.3V
J2
DNP
1000PF
6.81K C13
VW
OUT OUT OUT OUT
DNP R13
R9
EP P12 R23 5.49K R24 C20 390PF C23 DNP R30 0
VDIFF VSEN RTN DROOP DFB VO VSUM VIN VSS VDD
FB
C28
C29
ISL6261A
0.01UF
1UF
VCC_PRM
6.34K C3
OCSET
SOFT
U6
C31
R4
PMON/PGD_IN RBIAS VR_TT
FDE PMON RBIAS VR_TT NTC SOFT OCSET VW COMP FB
VID2 VID1 VID0 VCCP LGATE VSSP PHASE UGATE BOOT NC
2
+5V LGATE GND_POWER PHASE UGATE BOOT
OUT
10UF
10
0
P5
P4
IN IN
VCCSENSE VCORE
R5 0
COMP
R11
C12
P32
P26
10UF
C2
P9
1000PF
DROOP
R7
C6
C26
0
0.22UF
IN
VSSSENSE
330PF
RTN
P29
R12
P15
IN
C11
GND_POWER
R6 0
1000PF
C18
VSEN
C27
1UF
P11
P3
0.1UF C16
C15
4.53K R29 R28
DNP C25
P30 DNP
5.23K
C7 330PF
1K
3.57K 10K NTC R31
0.068UF C21
0.12UF C19
8200PF R27
29
FN6354.3 November 5, 2009
J3
J4
ISL6261A
DNP R8 DNP
P8
0
C9 150PF
R19 464K
R43 10K R44 10K R45 10K
3 1 S4 11 22 33
OFF ON
2
VR_ON
47PF C14
2.21K R25 0
VDIFF1
+3.3V
R33 2 R34 0 R35 0
1
J19
1 2 2 5V J16
IN
VR_ON1
1X3
P17
P21
DFB
R15
VIN
IN
VCC_PRM
IN
NOTE: RUN LGATE1 TRACE PARALLEL TO TRACE CONNECTING PGND1 AND SOURCE OF Q3 AND Q4.
TITLE:
VSUM
IN
ISL6261 EVAL1 CONTROLLER ENGINEER: JIA WEI DRAWN BY:
REV:
P22
?
DATE: MAR-14 SHEET: 1 OF
P36
0 C1 0.22UF
C33 DNP
2
R49 DNP D2
DNP
1
J20 4
3
1 2
3
1 2
C34 0.1UF
J5
P38
DNP
R54
R60
3
1 2
C35
J13
1
0.1UF C91 0.1UF C45 22UF C51 22UF C57 22UF C63 22UF C69 22UF C71 22UF C42 22UF C50 22UF C56 22UF C62 22UF C68 22UF C39 22UF C49 22UF C55 22UF C61 22UF C67 22UF
C43 330UF C44 330UF C90 330UF
OUT
ISL6261A
VSSSENSE
VCCSENSE
VSUM
OUT
R51 7.68K
IN
R50 0
L1 0.45UH DNP R52
IN
P39
VCC_PRM
J22 4
R53 0
BUS WIRE
P40
P41
J6
C38 22UF C48 22UF C54 22UF C60 22UF C66 22UF C70 22UF
C37 22UF C47 22UF C53 22UF C59 22UF C65 22UF
30
FN6354.3 November 5, 2009
Power Stage
IN
IN
IN
IN
BOOT
UGATE
PHASE
R48
LGATE
P35
Q1
IRF7821
IRF7832 IRF7832
Q2 Q4
VIN
C32 1UF 10UF C4 10UF C5 10UF C5B
R82
IRF7821
Q3
OUT
ISL6261A Eval1 Evaluation Board Schematics (Continued)
J21 4
56UF R83
1
56UF
22UF C46 22UF C52 22UF C58 22UF C64 22UF
GND_POWER
1
P37
C36
C40 330UF C41 330UF C89 330UF
VCORE
J14
1
OUT
OUT
ISL6261A Eval1 Evaluation Board Schematics (Continued)
Socket
AF24 AF21 AF19 AF16 AF13 AF11 AF8 AF6 AF3 AE26 AE23 AE19 AE16 AE14 AE11 AE8 AE4
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VCCSENSE
B26 AF7
OUT IN
VCORE
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17
F26 G2 G3 G5 G6 G22 G24 G25 H1 H2 H4 H5 H22 H23 H25 H26 J1 J3 J4 J23 J24 J26 K2 K3 K5 K22 K24 K25 L1 L2 L4 L5 L22 L23 L25 L26 M1 M3 M4 M23 M24 M26 N2 N3 N5 N22 N24 N25 P1 P2
VSSSENSE
VCCA VCCSENSE VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
PSI GTLREF VID6 VID5 VID4 VID3 VID2 VID1 VID0 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S
G21 J6 J21 K6 K21 M6 M21 N6 N21 R6 R21 T6 T21 V6 V21 W21 AF20 AF18 AF17 AF15 AF14 AF12 AF10 AF9 AE20 AE18 AE17 AE15 AE13 AE12 AE10 AE9 AD18 AD17 AD15 AD14 AD12 AD10 AD9 AD7 AC18 AC17 AC15 AC13 AC12 AC10 AC9 AC7 AB20 AB18 AB17 AB15 AB14 AB12 AB10 AB9 AB7 AA20 AA18
IN
S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S
OUT
A3 A5 A6 A21 A22 A24 A25 B1 B2 B3 B4 B5 B22 B23 B25 C1 C3 C4 C6 C7 C20 C21 C23 C24 C26 D2 D3 D5 D6 D7 D20 D21 D22 D24 D25 E1 E2 E4 E5 E22 E23 E25 E26 F1 F3 F4 F6 F21 F23 F24
S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S
INTEL_IMPV6
SOCKET1
COMP3 COMP1 COMP2 COMP0 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S
W22
V1 U26 U1 R26 AA4 AA3 AA1 Y26 Y25 Y23 Y22 Y5 Y4 Y2 Y1 W25 W24 W6 W5 W3 W2 V26 V24 V23 V4 V3 U25 U23 U22 U5 U4 U2 T25 T24 T22 T5 T3 T2 R24 R23 R4 R3 R1 P26 P25 P23 P22 P5 P4
A4 A8 A11 A14 A16 A19 A23 A26 B6 B8 B11 B13 B16 B19 B21 B24 C2 C5 C8 C11 C14 C16 C19 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F2 F5 F8 F11 F13 F16 F19 F22 F25 G1 G4 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AE1 AD25 AD22 AD19 AD16 AD13 AD11 AD8 AD5 AD2 AC24 AC21 AC19 AC16 AC14 AC11 AC8 AC6 AC3 AB26 AB23 AB19 AB16 AB13 AB11 AB8 AB4 AB1 AA25 AA22 AA19 AA16 AA14 AA11 AA8 AA5 AA2 Y24 Y21 Y6 Y3 W26 W23 W4 W1 V25 V22 V5 V2 U24 U21 U6 U3 T26 T23 T4 T1 R25 R22 R5 R2 P24 P21 P6 P3
PSI# AE6 OUT AD26 AE2 VID6 OUT AF2 VID5 OUT AE3 VID4 OUT AF4 VID3 OUT AE5 VID2 OUT AF5 VID1 OUT AD6 VID0 OUT AF26 AF25 AF23 AF22 AF1 AE25 AE24 AE22 AE21 AD24 AD23 AD21 AD20 AD4 AD3 AD1 AC26 AC25 AC23 AC22 AC20 AC5 AC4 AC2 AC1 AB25 AB24 AB22 AB21 AB6 AB5 AB3 AB2 AA26 AA24 AA23 AA21 AA6
K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 AE7
31
FN6354.3 November 5, 2009
INTEL_IMPV6
SOCKET1
INTEL_IMPV6
SOCKET1
ISL6261A
VSSSENSE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
GND_POWER
ISL6261A Eval1 Evaluation Board Schematics (Continued)
Dynamic Load
J12
GND_POWER
J11
+12V 1 2 3 4
C80 1UF
U5 VDD HB HO HS LO VSS LI HI
8 7 6 5
IN
HIP2100
2 1
3
1
R73 249
2
HUF76129D3S
3
0.12
R75
0.1 R76
3
49.9K
R71
3
2
C81
Q14
10UF
32
FN6354.3 November 5, 2009
VCORE
R74 249 D1 Q15
1 2 4 J23
BAV99
ISL6261A
+12V
+12V
GND_POWER
R72 499
1
2N7002
2
3
ON OFF
S5 1
ISL6261A Eval1 Evaluation Board Schematics (Continued)
Geyserville Transition Gen.
10K R84 10K R87 10K R90 10K R93 10K R96 10K R99 R81 10K
U10
1 2 3 4 5 6 7 8 9 10
U7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
14 14 13 13 12 12 11 11 10 10 99 88 MST7_SPST
G1 A1 A2 A3 A4 A5 A6 A7 A8 GND
U2
VCC G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
20 19 18 17 16 15 14 13 12 11
+3.3V_GEY
C72 0.1UF
32 35 36 37 42 43 44 1 12 13 38 39 40 41 2 3 4 5 25 26 27
HC540 U3
U8
1 2 3 4 5 6 7
1 2 3 4 5 6 7 8 9 10
P42
R68
MST7_SPST
GND
HC540 U4
Y8
11
DNP
A8
Y7
12
P45
1 2 3 4 5 6 7
14 14 13 13 12 12 11 11 10 10 99 88
G1 A1 A2 A3 A4 A5 A6 A7
VCC G2 Y1 Y2 Y3 Y4 Y5 Y6
20 19 18 17 16 15 14 13
+3.3V_GEY
C73 0.1UF
6 29
RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 NC NC RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE0 RE1 RE2 VSS VSS
10K R100
15PF
C85
VDD VDD
7 28
1UF
HCM49
0.01UF
IN
P43
CLK_EN#
R105
0 R67 DNP
C79
PIC16F874 +3.3V_GEYR69 R104 10K
RESETS8
1 2
4 3
EVQPA J28 1 12 2
+3.3V
C86 1UF U12
0
C87
C78
15PF
10K R85
10K R88
10K R91
10K R94
10K R97
R82
10K
RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 NC NC RA0 RA1 RA2 RA3 RA4 RA5 OSC1 OSC2 MCLR
8 9 10 11 14 15 16 17 33 34 19 20 21 22 23 24 30 31 18
VID0 VID1 VID2 VID3 VID4 VID5 VID6
OUT OUT OUT OUT OUT OUT OUT
R106 DNP
PSI# DPRSTP# PGD_IN VR_ON1
U11
1
OUT OUT OUT OUT
DIRECT
11 22 33
1X3
J7
DELAY DPRSLPVR
OUT
10K R101
10K R86
10K R89
10K R92
10K R95
10K R98
10K
R83
R65
10K
3
C77
BAV99
S3
5 6 7
10 9 8
6 7 8 9 10
A4 A5 A6 A7 A8 GND
Y3 Y4 Y5 Y6 Y7 Y8
R63
10K
4
11
5
16 15 14 13 12 11
6 7
9 8
DPRSLP S6
1
4 3
AC04
2 1
R70 0
R78 0
R79 0
0.1UF
C75
+3.3V_GEY
2
R66
10K
C84
DNP
C88
1
R55 R56 R57
10K 10K 10K 10K 10K 10K 10K
+3.3V_GEY
J25 12 2
R64
10K
PSI# S7
1 2
4 3
+3.3V
J24 1 1 2 2 +3.3V_GEY
C76
R58 R59 R61 R62
0.1UF
+3.3V_GEY
EVQPA J29 12 2
10K
PSI#
1
REV: TITLE: ISL6261 EVAL1 GEYSERVILLE TRANSITION GEN. ENGINEER: DATE: MARJIA WEI DRAWN BY: SHEET: 5
R102
DNP
HC540
LOOP
P44
MST7_SPST
EVQPA
R80 0
2 1
S9
3
12 11 10 9 8
12
4
A3
Y2
17
EVQPA
BAV99
A2
Y1
0.1UF
2
3
18
0.1UF
+3.3V_GEY
2
3
4 5
11 10
3A 3Y GND
3
33
FN6354.3 November 5, 2009
2
ISL6261A
+3.3V_GEY
VCC G2
20 19
R77
U9
1
1 2
1 2 3 4 5 6 7
14 14 13 13
G1 A1
+3.3V_GEY
C74
MODE TRANS
1
10K
4
1 2 3
S2
1A 1Y 2A 2Y
Vcc 6A 6Y 5A 5Y 4A 4Y
14 13 12
ISL6261A
Package Outline Drawing
L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06
4X 4.5 6.00 A B 6 PIN 1 INDEX AREA 30 31 36X 0.50 40 1 6 PIN #1 INDEX AREA
4 . 10 0 . 15 6.00
21 (4X) 0.15 20 TOP VIEW 40X 0 . 4 0 . 1 BOTTOM VIEW 11
10
0.10 M C A B 4 0 . 23 +0 . 07 / -0 . 05
SEE DETAIL "X" 0.10 C BASE PLANE SIDE VIEW ( 36X 0 . 5 ) SEATING PLANE 0.08 C C
0 . 90 0 . 1 ( 5 . 8 TYP ) ( 4 . 10 )
C ( 40X 0 . 23 ) ( 40X 0 . 6 ) TYPICAL RECOMMENDED LAND PATTERN
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX. DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
34
FN6354.3 November 5, 2009

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